1. Field of the Invention
The present invention relates to a semiconductor device having a memory cell region in which at least a field-effect transistor is formed and a non-memory cell region in which at least a bipolar transistor is formed, and a method of fabricating the same.
2. Description of the Related Art
An SRAM has a memory cell region and a peripheral circuit region. FIG. 18 shows an equivalent circuit of a memory cell of a high-resistance load type SRAM. A flip-flop 11 of this memory cell includes NMOS transistors 12 and 13 for driving and resistive elements 14 and 15 as loads. The memory cell is constituted by this flip-flop 11 and transfer NMOS transistors 16 and 17.
A ground line 21 is connected to the source regions of the NMOS transistors 12 and 13, and a power line 22 is connected to the resistive elements 14 and 15. Also, a word line 23 serves as a gate electrode of the NMOS transistors 16 and 17. A pair of non-inverted and inverted bit lines 24 and 25 are each connected to one of the source/drain regions of the NMOS transistors 16 and 17, respectively.
In an SRAM with this arrangement, the drain regions of the NMOS transistors 12 and 13 serve as storage node diffusion layers. Electric charge is stored in these drain regions, and data is stored by setting these drain regions at a predetermined potential. However, if xcex1 rays emitted from a slight amount of a radioactive element such as uranium or thorium contained in a packaging mold resin or the like enter a semiconductor base, electron-hole pairs are generated by impact ionization by the xcex1 rays.
Holes of the generated electron-hole pairs flow in a grounded P-well in the semiconductor base. Electrons are trapped in the drain regions of the NMOS transistors 12 and 13 and the like to which a positive voltage is applied. As a consequence, the amount of electric charge stored in these drain regions varies, and this can cause a soft error in which the potential of these drain regions is inverted to invert the stored data.
Especially when xcex1 rays penetrate through the drain regions and their depletion layers of the NMOS transistors 12 and 13, these depletion layers instantaneously extend to bring about a funneling phenomenon. Consequently, the electron trap efficiency increases, and this can further increase the possibility of a soft error.
It is, therefore, being attempted to add a capacitor between the storage nodes to trap electrons generated by the impact ionization into this capacitor (e.g., Japanese Patent Laid-Open No. 62-154296), or to form a P+-type buried diffusion layer, as a potential barrier against electrons, in a memory cell region to thereby prevent diffused electrons from moving into the depletion layers (e.g., Japanese Patent Laid-Open No. 62-245660).
A bipolar transistor is formed in a peripheral circuit region or the like of an SRAM. As is well known, when the base and emitter regions of a bipolar transistor are formed by rapid thermal annealing such as halogen lamp annealing, the base width which is the difference between the depths of the base and emitter regions can be accurately controlled, and consequently the characteristics of the bipolar transistor, particularly the high-frequency characteristics such as the cut-off frequency can be improved.
The structure in which a capacitor is additionally formed as described in Japanese Patent Laid-Open No. 62-154296 is effective to a semiconductor device, such as a TFT load type SRAM, using two conductive layers as load elements. However, it is difficult to apply this structure to a semiconductor device, such as a high-resistance load type SRAM, using only one conductive layer as a load element, since a capacitor is difficult to form.
In the case of the structure in which a P+-type buried diffusion layer is formed in a memory cell region as described in Japanese Patent Laid-Open No. 62-245660, it is necessary to add fabrication steps of additionally forming this P+-type buried diffusion layer. Therefore, it is difficult to increase the soft error resistance while suppressing an increase in the fabrication cost.
In addition, when the P+-type buried diffusion layer is formed by high-energy ion implantation, defective layers may locally remain in a semiconductor base due to ion implantation damage even if annealing for recovering the crystallinity is performed after the ion implantation. Accordingly, it is difficult to increase the soft error resistance without lowering the storage retention ability on a one-bit level.
Furthermore, when the base and emitter regions are formed by rapid thermal annealing in order to improve the characteristics of a bipolar transistor in a peripheral circuit region of an SRAM or the like, an impurity in load elements such as the resistive elements 14 and 15 diffuses, and the characteristics of the load elements vary. Also, a gate insulating film deteriorates, and hot carriers are injected into the gate insulating film. Consequently, the characteristics such as the gate withstand voltage and the life of a MOS transistor in a memory cell region or the like easily deteriorate.
As described above, a large number of conventional methods have been reported which apply rapid thermal annealing to a simple device including only a bipolar transistor to improve its characteristics. However, it is conventionally difficult, by applying rapid thermal annealing to a composite device such as an SRAM having a bipolar transistor in a peripheral circuit region, to fabricate a semiconductor device in which elements such as a load element and a MOS transistor, other than the bipolar transistor, also have excellent characteristics.
A semiconductor device according to the present invention is a semiconductor device in which a memory cell region having a first N-type field-effect transistor and a non-memory cell region having an NPN bipolar transistor and a second N-type field-effect transistor are formed in the same semiconductor base, comprising: a first N-type buried diffusion layer formed in the semiconductor base of the memory cell region; and a second N-type buried diffusion layer forming a portion of a collector region of the bipolar transistor; wherein a threshold voltage of the first field-effect transistor is higher than a threshold voltage of the second field-effect transistor.
In the semiconductor device according to the present invention, the first buried diffusion layer preferably extends by 0.5 to 2 xcexcm from the memory cell region into the non-memory cell region.
In the semiconductor device according to the present invention, first and second plug regions exposed to a surface of the semiconductor base are preferably connected to the first and second buried diffusion layers, respectively.
In the semiconductor device according to the present invention, it is preferable that the semiconductor base be composed of a semiconductor substrate and a 0.5- to 1-xcexcm thick semiconductor layer formed on the semiconductor substrate, and the first and second buried diffusion layers be formed in a surface portion of the semiconductor substrate.
A first semiconductor device fabrication method according to the present invention is a method of fabricating a semiconductor device in which a memory cell region having a first N-type field-effect transistor and a non-memory cell region having an NPN bipolar transistor and a second N-type field-effect transistor are formed in the same semiconductor base, comprising the steps of simultaneously forming first and second N-type diffusion layers in surface portions of a semiconductor substrate of the memory cell region and a region in which the bipolar transistor is to be formed, respectively, growing an epitaxial layer on the semiconductor substrate to form the semiconductor base and convert the diffusion layers into buried diffusion layers, and making a threshold voltage of the first field-effect transistor higher than a threshold voltage of the second field-effect transistor.
The first semiconductor device fabrication method according to the present invention preferably further comprises the steps of simultaneously doping a P-type impurity into channel regions of the first and second field-effect transistors, and doping a P-type impurity only into the channel region of the first field-effect transistor.
A second semiconductor device fabrication method according to the present invention is a method of fabricating a semiconductor device having a memory cell region in which a flip-flop including a field-effect transistor and a load element is formed and a non-memory cell region in which a bipolar transistor is formed, comprising the steps of forming at least a base region and an emitter region of the bipolar transistor by rapid thermal annealing, and forming the load element after the rapid thermal annealing.
The second semiconductor device fabrication method according to the present invention preferably further comprises the steps of forming the load element connected to a storage node diffusion layer of the flip-flop, and doping phosphorus into the connecting portion.
In the second semiconductor device fabrication method according to the present invention, a resistive element can be used as the load element.
In the second semiconductor device fabrication method according to the present invention, a field-effect transistor having a conductivity type opposite to a conductivity type of the field-effect transistor can be used as the load element, and a gate electrode of the field-effect transistor having the opposite conductivity type can be connected to the storage node diffusion layer.
In the second semiconductor device fabrication method according to the present invention, a temperature of the rapid thermal annealing is preferably at 1000 to 1150xc2x0 C.
In the semiconductor device according to the present invention, the first N-type buried diffusion layer is formed in the memory cell region. As long as a positive voltage is applied to this first buried diffusion layer, therefore, even if a rays which generate electron-hole pairs by impact ionization enter the semiconductor base, holes flow through the semiconductor base, and electrons trapped in the first buried diffusion layer flow through this first buried diffusion layer. Accordingly, it is possible to suppress variations in the amount of electric charge in the diffusion layer of the first field-effect transistor in the memory cell region.
In addition, the threshold voltage of the first field-effect transistor in the memory cell region is higher than the threshold voltage of the second field-effect transistor in the non-memory cell region. Therefore, it is possible to prevent an increase in the sub-threshold current in the first field-effect transistor resulting from upward diffusion of the impurity from the first buried diffusion layer in the memory cell region.
Generally, if the sub-threshold current in a field-effect transistor constituting a memory cell increases, it is necessary to decrease the resistance of a load element constituting the memory cell in order to ensure stable storage operation. As a consequence, the standby current in the memory cell region determined by this resistance increases. Since, however, an increase in the sub-threshold current in the first field-effect transistor in the memory cell region is prevented as described above, an increase in the standby current in the memory cell region is also prevented.
Furthermore, both the first buried diffusion layer in the memory cell region and the second buried diffusion layer which forms a portion of the collector region of the bipolar transistor in the non-memory cell region are of N type. Accordingly, the first buried diffusion layer in the memory cell region and the second buried diffusion layer in the non-memory cell region can be simultaneously formed.
Also, when the first buried diffusion layer extends by 0.5 to 2 xcexcm from the memory cell region into the non-memory cell region, it is possible to suppress an increase in the necessary area while suppressing variations in the charge amount in the diffusion layer of the first field-effect transistor even in a peripheral portion of the memory cell region.
When the first plug region exposed to the surface of the semiconductor base is connected to the first buried diffusion layer in the memory cell region, a positive voltage can be easily applied to this first buried diffusion layer. Additionally, since the second plug region is connected to the second buried diffusion layer in the non-memory cell region, the first plug region can be formed simultaneously with the second plug region.
The smaller the thickness of the semiconductor layer on the first and second buried diffusion layers, the lower the soft error occurrence rate in the memory cell. Conversely, the larger the thickness of this semiconductor layer, the larger the open-base, grounded-emitter maximum collector voltage and the collector current in the bipolar transistor. When the thickness of this semiconductor layer is 0.5 to 1 xcexcm, the soft error occurrence rate is low, and the open-base, grounded-emitter maximum collector voltage and the collector current are large.
In the first semiconductor device fabrication method according to the present invention, after first and second diffusion layers are formed in a surface portion of a semiconductor substrate, an epitaxial layer is grown on this semiconductor substrate to form first and second buried diffusion layers in a semiconductor base. That is, the first and second buried diffusion layers are not formed by high-energy ion implantation. Accordingly, no defective layers locally remain in the semiconductor base due to ion implantation damage.
In addition, the first buried diffusion layer in a memory cell region and the second buried diffusion layer which forms a portion of the collector region of a bipolar transistor in a non-memory cell region are simultaneously formed. Therefore, the number of fabrication steps is not increased by the formation of the first buried diffusion layer in the memory cell region.
A P-type impurity is simultaneously doped into the channel regions of both first and second field-effect transistors, and a P-type impurity is doped only into the channel region of the first field-effect transistor, thereby making the threshold voltage of the first field-effect transistor higher than the threshold voltage of the second field-effect transistor. This decreases the number of masks compared to a case where a P-type impurity is separately doped into channel regions of first and second field-effect transistors.
In the second semiconductor device fabrication method according to the present invention, at least the base and emitter regions of a bipolar transistor are formed by rapid thermal annealing. Therefore, the base width of the bipolar transistor can be accurately controlled. Additionally, since a load element is formed after the rapid thermal annealing, diffusion of an impurity in the load element can be prevented.
Also, phosphorus is doped into a connecting portion between a storage node diffusion layer and a load element of a flip-flop. Since phosphorus has a larger diffusion coefficient than that of, e.g., arsenic, even if the load element is formed after the rapid thermal annealing, phosphorus can be well diffused by annealing after the formation of the load element. Consequently, it is possible to decrease a change in the impurity concentration in the storage node diffusion layer and reduce the junction leakage in this storage node diffusion layer.
When the temperature of the rapid thermal annealing for forming at least the base and emitter regions of the bipolar transistor is set at 1000 to 1150xc2x0 C., the base width of the bipolar transistor can be accurately controlled. Additionally, it is possible to prevent deterioration of a gate insulating film of the field-effect transistor and injection of hot carriers into the gate insulating film.